The present disclosure generally relates to semiconductor device processing, and more specifically, to dual damascene structures.
Copper-based chips are semiconductor integrated circuits that use copper for interconnections. Chips using copper interconnects can have smaller metal components than chips that use aluminum interconnects because copper is a better conductor than aluminum. Copper-based chips also use less energy to pass electricity through them.
Copper-based chips are patterned using additive patterning, also called damascene processing or dual damascene processing. In damascene processing, generally, the underlying silicon oxide insulating layer is patterned with open trenches where the conductor should be. A thick coating of copper that overfills the trenches is deposited on the silicon oxide. Chemical-mechanical planarization (CMP) is used to remove the copper that extends above the top of the insulating layer. Copper remaining within the trenches of the silicon oxide layer is not removed and becomes the patterned conductor.
Damascene processes generally form and fill a single feature with copper per damascene stage. Dual damascene processes generally form and fill two features with copper at once, e.g., a trench overlying a via in a dielectric material may both be filled with a single copper deposition using dual-damascene processing. In integrated circuits, a via is a small opening in the dielectric layer that allows a conductive connection between two metal layers.